PIC16C63A-04I/SO【PDF 16/184 页】IC MCU OTP 4KX14 PWM 28SOIC

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112

SAM7S Series [DATASHEET]

6175M–ATARM–26-Oct-12

When programming is complete, the bit FRDY bit in the Flash Programming Status Register (MC_FSR) rises. If an

interrupt has been enabled by setting the bit FRDY in MC_FMR, the interrupt line of the Memory Controller is

activated.

Two errors can be detected in the MC_FSR register after a programming sequence:

Programming Error: A bad keyword and/or an invalid command have been written in the MC_FCR register.

Lock Error: At least one lock region to be erased is protected. The erase command has been refused and no

page has been erased. A Clear Lock Bit command must be executed previously to unlock the corresponding

lock regions.

19.2.4.3

Lock Bit Protection

Lock bits are associated with several pages in the embedded Flash memory plane. This defines lock regions in the

embedded Flash memory plane. They prevent writing/erasing protected pages.

After production, the device may have some embedded Flash lock regions locked. These locked regions are

reserved for a default application. Refer to the product definition section for the default embedded Flash mapping.

Locked sectors can be unlocked to be erased and then programmed with another application or other data.

The lock sequence is:

The Flash Command register must be written with the following value:

(0x5A << 24) | (lockPageNumber << 8 & PAGEN) | SLB

lockPageNumber is a page of the corresponding lock region.

When locking completes, the bit FRDY in the Flash Programming Status Register (MC_FSR) rises. If an

interrupt has been enabled by setting the bit FRDY in MC_FMR, the interrupt line of the Memory Controller is

activated.

A programming error, where a bad keyword and/or an invalid command have been written in the MC_FCR register,

may be detected in the MC_FSR register after a programming sequence.

It is possible to clear lock bits that were set previously. Then the locked region can be erased or programmed. The

unlock sequence is:

The Flash Command register must be written with the following value:

(0x5A << 24) | (lockPageNumber << 8 & PAGEN) | CLB

lockPageNumber is a page of the corresponding lock region.

When the unlock completes, the bit FRDY in the Flash Programming Status Register (MC_FSR) rises. If an

interrupt has been enabled by setting the bit FRDY in MC_FMR, the interrupt line of the Memory Controller is

activated.

A programming error, where a bad keyword and/or an invalid command have been written in the MC_FCR register,

may be detected in the MC_FSR register after a programming sequence.

The Unlock command programs the lock bit to 1; the corresponding bit LOCKSx in MC_FSR reads 0. The Lock

command programs the lock bit to 0; the corresponding bit LOCKSx in MC_FSR reads 1.

Note:

Access to the Flash in Read Mode is permitted when a Lock or Unlock command is performed.

19.2.4.4

General-purpose NVM Bits

General-purpose NVM bits do not interfere with the embedded Flash memory plane. (Does not apply to EFC1 on

the SAM7S512.) These general-purpose bits are dedicated to protect other parts of the product. They can be set

(activated) or cleared individually. Refer to the product definition section for the general-purpose NVM bit action.

The activation sequence is:

Start the Set General Purpose Bit command (SGPB) by writing the Flash Command Register with the SEL

command and the number of the general-purpose bit to be set in the PAGEN field.

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